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Streamline TEM Lamella Preparation from 7nm Devices with Tescan SOLARIS X 2 

Perform TEM lamella preparation on 7nm node transistors using Tescan SOLARIS X 2 with in-situ delayering and thinning that maintain structural fidelity and eliminate air exposure.

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Gas-assisted delayering and TEM lamella preparation from a 7nm chip
Gas-assisted delayering and TEM lamella preparation from a 7nm chip
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Perform Site-Specific TEM Lamella Prep from 7nm Chips with In-Situ Delayering and Ga-Free Precision 

7nm logic devices demand structural accuracy at nanoscale dimensions — particularly across densely packed contact and transistor layers. Sample preparation methods that require multiple systems or air exposure increase the risk of layer damage, oxidation, and misalignment.

Tescan SOLARIS X 2 integrates gas-assisted delayering and Xe⁺ plasma FIB milling in a single, air-free workflow. Isolate sub-20 nm TEM lamella directly from targeted regions, using passive voltage contrast (PVC) and low-keV SEM end-pointing to navigate multilayer stacks with confidence.

Why Prepare TEM Lamella from 7nm Node Devices

with Tescan SOLARIS X 2 FIB-SEM

01
Root of the Problem

Why Standard TEM Prep Workflows Fall Short on 7nm Node Devices

Preparing TEM lamella from 7nm logic structures requires nanometer-scale precision. But standard workflows — involving multiple systems and air breaks — often introduce contamination, misalignment, or structural damage. Reaching contact layers without overshooting is difficult, especially when endpointing lacks accuracy.

Transistor features at 7nm are deeply embedded and sensitive to ion damage. Even slight missteps during trenching or thinning can distort key regions or degrade imaging resolution.

Tescan SOLARIS X 2 addresses these issues with a tightly integrated, application-specific workflow:

  • In-situ delayering and thinning avoid air exposure
  • Inverted geometry improves lamella stability
  • SEM-based endpointing ensures targeting accuracy
  • Xe⁺ plasma FIB prevents Ga contamination
  • Final 1 keV polish maintains structural integrity

Achieve reliable, repeatable sub-20 nm lamella prep ready for high-resolution analysis using SOLARIS X 2.

02
Materials and Methods

How TEM Lamella Were Prepared from 7nm Devices Using Tescan SOLARIS X 2 FIB-SEM

A 7nm FinFET device was selected to demonstrate integrated delayering and lamella preparation. The region of interest was identified using passive voltage contrast (PVC) and low-keV SEM imaging to accurately locate the contact and transistor layers.

Delayering was carried out using Xe⁺ plasma FIB with Nanoflat chemistry, enabling controlled removal of metal layers from M10 to contact. A protective Pt cap was deposited prior to trenching and thinning.

Lamella were lifted out in-situ using the OptiLift™ rotational nanomanipulator. Inverted geometry supported mechanical stability during thinning, with a final 1 keV FIB polish achieving ~16.5 nm thickness.

This process enables you to prepare high-quality, repeatable lamella for TEM analysis of transistor-level structures.

03
Results and Discussion

High-Resolution TEM Analysis of Contact and Transistor Features in 7nm Devices

Tescan SOLARIS X 2 FIB-SEM enabled consistent preparation of sub-20 nm lamella from contact-layer and active transistor regions of a 7nm FinFET device. The use of inverted geometry, combined with low-kV final polishing, preserved the integrity of metal stacks, gate structures, and dielectric boundaries across the lamella.

TEM imaging revealed clean interfaces and low amorphization, supporting clear visualization of critical transistor features such as contact alignment, channel geometry, and gate-to-contact connectivity. Thinning precision allowed for structural assessment at the nanometer scale, even in densely packed device regions.

Contact-layer lamella showed well-defined metal transitions and minimal curtaining, while transistor cross-sections retained contrast across poly-Si gates and surrounding dielectrics. Cross-lamella validation confirmed thickness uniformity down to ~16.5 nm.

With this workflow, structural inspection, process verification, and localized defect analysis at the 7nm node become highly effective. This delivered the reproducibility and accuracy required for modern semiconductor engineering.

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Tescan Instruments & Technology

Used in This Workflow

Tescan SOLARIS X 2 FIB-SEM 

TESCAN SOLARIS X 2 FIB-SEM delivers the precision, control, and integration required for preparing sub-20 nm TEM lamella from 7nm node devices.

 

The Xe⁺ plasma-based system combines gas-assisted delayering, trenching, and thinning within a single, in-situ workflow—eliminating air exposure and reducing variability.

 

OptiLift™ nanomanipulation supports stable lamella handling, while low-keV final polishing ensures structural integrity for high-resolution imaging.

  • Integrated Xe⁺ plasma FIB-SEM platform: Complete TEM preparation without transferring between systems
  • Gas-assisted delayering: Remove layers from M10 to contact with control and repeatability
  • In-situ lift-out with OptiLift™: Reduce mechanical stress and contamination during lamella transfer
  • Sub-20 nm lamella preparation: Achieve transistor-level resolution suitable for HR-TEM or STEM
  • Inverted geometry and 1 keV final thinning: Minimize curtaining and preserve structural accuracy across layers
SOLARIS-X2
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Where can you find us:

Tescan
Libušina třída 21
623 00 Brno 
Czech Republic

info@Tescan.com 

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