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Simplify Sub-20 nm Node Delayering for In-Situ Nanoprobing with Tescan AMBER X 2

Use Tescan AMBER X 2 with Mistral plasma FIB to perform Sub-20 nm node delayering that enables precise endpoint detection and in-situ nanoprobing of advanced transistors.

Delayering sub-20 nm nodes for in-situ nanoprobing with TESCAN AMBER X 2
Delayering sub-20 nm nodes for in-situ nanoprobing with TESCAN AMBER X 2
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Achieve Uniform Planarity and Reliable Probing through Sub-20 nm Node Delayering with Tescan AMBER X 2

Sub-20 nm logic and memory devices feature intricate multilayer architectures, where even slight over-milling or surface roughness can compromise transistor integrity. Low-k dielectrics and copper interconnects are especially prone to damage, making uniform delayering and endpoint accuracy critical for reliable electrical analysis.

Tescan AMBER X 2 with Mistral plasma FIB and real-time SE signal end pointing delivers precise Sub-20 nm node delayering. Achieve planar surfaces below 5 nm RMS roughness, maintain dielectric compatibility, and prepare contamination-free structures ready for in-situ nanoprobing and electrical failure analysis. 

Why Perform Sub-20 nm Node Delayering

with Tescan AMBER X 2

01
Root of the Problem

Why Conventional Delayering Workflows Fail at Sub-20 nm Nodes

Advanced logic and memory devices at sub-20 nm nodes demand extremely precise delayering. Yet traditional Ga+ FIB workflows often produce rough surfaces, struggle with endpoint control, and expose sensitive dielectrics to damage.

Oxidation of copper interconnects and contamination during probing further reduce reliability. When engineers must switch between separate systems for delayering, conditioning, and probing, efficiency drops, and device integrity is at risk.

Tescan AMBER X 2 Plasma FIB-SEM addresses these issues by integrating high-throughput Xe+ milling with advanced delayering workflows in a single instrument:

  • Real-time SE signal end pointing ensures accurate transistor layer exposure
  • Mistral plasma FIB supports precise layer-by-layer removal
  • Nanoflat etch delivers <5 nm RMS roughness for planar surfaces
  • A-Maze™ gas chemistry enables selective copper removal without oxidation
  • Contamination-free delayering preserves electrical measurement integrity

02
Materials and Methods

How Sub-20 nm Node Delayering Was Performed Using Tescan AMBER X 

A 14 nm Intel Skylake CPU and advanced 7 nm/5 nm CMOS devices were selected to demonstrate precise delayering and in-situ nanoprobing. Initial surface milling was carried out using Xe+ plasma FIB under iFIB+™ control, ensuring layer-by-layer removal across large device areas. Real-time SE signal end pointing was used to identify transistor layers and prevent over-milling.

Nanoflat etch was applied to achieve surface planarity under 5 nm RMS, ensuring reliable probe contact on sensitive low-k dielectrics. A-Maze™ gas chemistry provided selective copper removal while maintaining oxidation-free surfaces.

Following delayering, in-situ nanoprobing was performed directly within the SEM chamber using Kleindiek PS8 probes. Electrical measurements such as EBAC and conductive AFM were integrated into the workflow, enabling transistor-level validation of PMOS and NMOS structures without contamination.

03
Results and Discussion

Integrated Delayering and Nanoprobing Reveals Electrical Pathways in Advanced Nodes

Tescan AMBER X 2 with Xe+ plasma FIB enabled uniform, large-area delayering of advanced logic and memory devices down to the sub-20 nm node. Real-time SE endpointing allowed accurate exposure of transistor layers, preventing both over-milling and incomplete removal. The resulting surfaces achieved <5 nm RMS roughness, ensuring stable and reproducible contact for nanoprobing.

In-situ electrical probing of 7 nm and 5 nm CMOS devices revealed transistor-level behavior by contacting gate, source, and drain directly inside the SEM chamber. EBAC imaging mapped conductive pathways with high fidelity, while conductive AFM confirmed contamination-free signal integrity.

Selective copper removal using A-Maze™ chemistry provided oxidation-free interconnect exposure, and nanoflat etch maintained dielectric compatibility. Together, these methods delivered reliable measurements of PMOS and NMOS transistor performance.

The integrated workflow significantly outperformed conventional Ga+ FIB delayering by reducing artifacts, improving measurement reproducibility, and enabling seamless progression to TEM or AFM characterization.

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Tescan Instruments & Technology

Used in This Workflow

Tescan AMBER X 2 Plasma FIB-SEM

Tescan AMBER X 2 Plasma FIB-SEM combines a high-throughput Xe+ plasma FIB with a field-free UHR SEM column, enabling large-area delayering and ultra-high-resolution imaging in a single workflow.

Designed for advanced semiconductor failure analysis, it delivers precise control, uniform planarity, and direct integration with in-situ nanoprobing.

You can delayer complex logic and memory devices, expose transistor layers with real-time endpoint detection, and prepare contamination-free surfaces optimized for electrical probing and TEM readiness.

  • Xe+ plasma FIB: high-throughput milling for large-area delayering of sub-20 nm nodes

  • Field-free UHR SEM: ultra-high-resolution imaging without magnetic interference

  • Mistral Plasma FIB: low keV gentle layer removal during delayering

  • Real-time SE signal end pointing: accurate transistor exposure without over-milling

  • Nanoflat etch: dielectric surface smoothing below 5 nm RMS roughness

  • Nanoflat gas chemistry: selective copper removal with oxidation-free surfaces

  • In-situ nanoprobing compatibility: seamless integration with Kleindiek PS8 for electrical analysis
AMBER-X2

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Where can you find us:

Tescan
Libušina třída 21
623 00 Brno 
Czech Republic

info@Tescan.com 

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