Streamline TEM Lamella Preparation from 7nm Devices with Tescan SOLARIS X  

Perform Site-Specific TEM Lamella Prep from 7nm Chips with In-Situ Delayering and Ga-Free Precision

7nm logic devices demand structural accuracy at nanoscale dimensions — particularly across densely packed contact and transistor layers. Sample preparation methods that require multiple systems or air exposure increase the risk of layer damage, oxidation, and misalignment.

Tescan SOLARIS X integrates gas-assisted delayering and Xe⁺ plasma FIB milling in a single, air-free workflow. Isolate sub-20 nm TEM lamella directly from targeted regions, using passive voltage contrast (PVC) and low-keV SEM end-pointing to navigate multilayer stacks with confidence.

Why Prepare TEM Lamella from 7nm Node Devices with Tescan SOLARIS X FIB-SEM?

Achieve Uniform Delayering Across 7nm Devices with Nanoflat Chemistry

Maintain planarity across large areas of advanced FinFET chips. Nanoflat-assisted gas delayering enables controlled layer removal from M10 to contact, preserving contrast and minimizing topography variation.

Resolve Fin-Level Structures with High-Quality Fin-Cut TEM Lamella

Target vertical transistor features with nanometer precision. Enable precise targeting of vertical transistor features with fin-cut geometry for structural analysis at nanometer resolution.

Improve Thinning Uniformity with Inverted Lamella Geometry

Minimize curtaining and enhance structural stability during final thinning. Invert the sample orientation to maintain lamella flatness and support sub-20 nm precision in gate-to-contact cross-sections.

Ensure Lamella Stability During Lift-Out with Inverted Geometry

Position the lamella for improved handling and mechanical support during extraction. Inverted lift-out geometry enhances precision and minimizes stress on ultra-thin sections during transfer to the TEM grid.

Validate Final Lamella Thickness with EELS for High-Resolution TEM

Confirm sub-20 nm uniformity across targeted regions. Use electron energy loss spectroscopy (EELS) to measure lamella thickness and ensure suitability for atomic-level imaging.

Contents 

1. Root of the Problem

Why Standard TEM Prep Workflows Fall Short on 7nm Node Devices

Preparing TEM lamella from 7nm logic structures requires nanometer-scale precision. But standard workflows — involving multiple systems and air breaks — often introduce contamination, misalignment, or structural damage. Reaching contact layers without overshooting is difficult, especially when endpointing lacks accuracy.

Transistor features at 7nm are deeply embedded and sensitive to ion damage. Even slight missteps during trenching or thinning can distort key regions or degrade imaging resolution.

Tescan SOLARIS X addresses these issues with a tightly integrated, application-specific workflow:

• In-situ delayering and thinning avoid air exposure
• Inverted geometry improves lamella stability
• SEM-based endpointing ensures targeting accuracy
• Xe⁺ plasma FIB prevents Ga contamination
• Final 1 keV polish maintains structural integrity

Achieve reliable, repeatable sub-20 nm lamella prep ready for high-resolution analysis using SOLARIS X.

2. Materials and Methods

How TEM Lamella Were Prepared from 7nm Devices Using Tescan SOLARIS X FIB-SEM

A 7nm FinFET device was selected to demonstrate integrated delayering and lamella preparation. The region of interest was identified using passive voltage contrast (PVC) and low-keV SEM imaging to accurately locate the contact and transistor layers.

Delayering was carried out using Xe⁺ plasma FIB with Nanoflat chemistry, enabling controlled removal of metal layers from M10 to contact. A protective Pt cap was deposited prior to trenching and thinning.

Lamella were lifted out in-situ using the OptiLift™ rotational nanomanipulator. Inverted geometry supported mechanical stability during thinning, with a final 1 keV FIB polish achieving ~16.5 nm thickness.

This process enables you to prepare high-quality, repeatable lamella for TEM analysis of transistor-level structures.

3. Results and Discussion

High-Resolution TEM Analysis of Contact and Transistor Features in 7nm Devices

Tescan SOLARIS X FIB-SEM enabled consistent preparation of sub-20 nm lamella from contact-layer and active transistor regions of a 7nm FinFET device. The use of inverted geometry, combined with low-kV final polishing, preserved the integrity of metal stacks, gate structures, and dielectric boundaries across the lamella.

TEM imaging revealed clean interfaces and low amorphization, supporting clear visualization of critical transistor features such as contact alignment, channel geometry, and gate-to-contact connectivity. Thinning precision allowed for structural assessment at the nanometer scale, even in densely packed device regions.

Contact-layer lamella showed well-defined metal transitions and minimal curtaining, while transistor cross-sections retained contrast across poly-Si gates and surrounding dielectrics. Cross-lamella validation confirmed thickness uniformity down to ~16.5 nm.

With this workflow, structural inspection, process verification, and localized defect analysis at the 7nm node become highly effective. This delivered the reproducibility and accuracy required for modern semiconductor engineering.