Simplify Sub-20 nm Node Delayering for In-Situ Nanoprobing with TESCAN AMBER X 

Achieve Uniform Planarity and Reliable Probing through Sub-20 nm Node Delayering with Tescan AMBER X

Sub-20 nm logic and memory devices feature intricate multilayer architectures, where even slight over-milling or surface roughness can compromise transistor integrity. Low-k dielectrics and copper interconnects are especially prone to damage, making uniform delayering and endpoint accuracy critical for reliable electrical analysis.

Tescan AMBER X with iFIB+™ control and real-time SE signal end pointing delivers precise Sub-20 nm node delayering. Achieve planar surfaces below 5 nm RMS roughness, maintain dielectric compatibility, and prepare contamination-free structures ready for in-situ nanoprobing and electrical failure analysis.

Why Perform Sub-20 nm Node Delayering with Tescan AMBER X?

Achieve Large-Area Uniform Delayering in Advanced CPUs

Perform plasma FIB delayering of 14 nm logic devices with high throughput and surface planarity. Prepare large uniform regions for in-situ nanoprobing and advanced electrical failure analysis.

Enable Reliable Electrical Probing at the 7 nm Technology Node

Perform in-situ nanoprobing directly within the SEM chamber to access PMOS and NMOS transistors. Achieve contamination-free electrical measurements that support advanced failure analysis and device validation.

Directly Probe Gate, Source, and Drain in 5 nm CMOS Devices

Access transistor-level electrical behavior by nanoprobing gate, source, and drain contacts within advanced CMOS structures. Validate device performance and isolate electrical faults at the smallest technology nodes.

Perform Large-Area Uniform Delayering of 3D NAND Devices

Use Xe plasma FIB to mill extensive regions of 3D NAND with consistent planarity and surface smoothness. Prepare wide, artifact-free delayered areas that are ready for electrical probing and structural analysis.

Improve Selectivity and Surface Quality with Gas-Assisted Delayering

Enhance plasma FIB milling using A-Maze™ gas chemistry for controlled copper removal and dielectric smoothing. Achieve planar delayering with 5 nm RMS roughness, optimized.

Contents 

1. Root of the Problem

Why Conventional Delayering Workflows Fail at Sub-20 nm Nodes

Advanced logic and memory devices at sub-20 nm nodes demand extremely precise delayering. Yet traditional Ga FIB workflows often produce rough surfaces, struggle with endpoint control, and expose sensitive dielectrics to damage.

Oxidation of copper interconnects and contamination during probing further reduce reliability. When engineers must switch between separate systems for delayering, conditioning, and probing, efficiency drops, and device integrity is at risk.

Tescan AMBER X Plasma FIB-SEM addresses these issues by integrating high-throughput Xe+ milling with advanced delayering workflows in a single instrument:

• Real-time SE signal end pointing ensures accurate transistor layer exposure
• iFIB+™ control supports precise layer-by-layer removal
• Nanoflat etch delivers <5 nm RMS roughness for planar surfaces
• A-Maze™ gas chemistry enables selective copper removal without oxidation
• Contamination-free delayering preserves electrical measurement integrity

2. Materials and Methods

How Sub-20 nm Node Delayering Was Performed Using Tescan AMBER X

A 14 nm Intel Skylake CPU and advanced 7 nm/5 nm CMOS devices were selected to demonstrate precise delayering and in-situ nanoprobing. Initial surface milling was carried out using Xe+ plasma FIB under iFIB+™ control, ensuring layer-by-layer removal across large device areas. Real-time SE signal end pointing was used to identify transistor layers and prevent over-milling.

Nanoflat etch was applied to achieve surface planarity under 5 nm RMS, ensuring reliable probe contact on sensitive low-k dielectrics. A-Maze™ gas chemistry provided selective copper removal while maintaining oxidation-free surfaces.

Following delayering, in-situ nanoprobing was performed directly within the SEM chamber using Kleindiek PS8 probes. Electrical measurements such as EBAC and conductive AFM were integrated into the workflow, enabling transistor-level validation of PMOS and NMOS structures without contamination.

3. Results and Discussion

Integrated Delayering and Nanoprobing Reveals Electrical Pathways in Advanced Nodes

Tescan AMBER X with Xe plasma FIB enabled uniform, large-area delayering of advanced logic and memory devices down to the sub-20 nm node. Real-time SE endpointing allowed accurate exposure of transistor layers, preventing both over-milling and incomplete removal. The resulting surfaces achieved <5 nm RMS roughness, ensuring stable and reproducible contact for nanoprobing.

In-situ electrical probing of 7 nm and 5 nm CMOS devices revealed transistor-level behavior by contacting gate, source, and drain directly inside the SEM chamber. EBAC imaging mapped conductive pathways with high fidelity, while conductive AFM confirmed contamination-free signal integrity.

Selective copper removal using A-Maze™ chemistry provided oxidation-free interconnect exposure, and nanoflat etch maintained dielectric compatibility. Together, these methods delivered reliable measurements of PMOS and NMOS transistor performance.

The integrated workflow significantly outperformed conventional Ga FIB delayering by reducing artifacts, improving measurement reproducibility, and enabling seamless progression to TEM or AFM characterization.