At ISTFA 2025, engineers and analysts confronted the practical realities of today’s semiconductor failure analysis challenges. Advanced packaging trends, from chiplet designs to stacked interconnects, continued to reshape expectations for accuracy and preparation speed. These shifts renewed attention on laser sample preparation as a way to achieve stable, repeatable results across diverse materials. With that context, we can look more closely at what this year’s ISTFA revealed and how the event reflected the industry’s direction.
ISTFA 2025 took place from November 16 to 20 at the Pasadena Convention Center in California. The International Symposium for Testing and Failure Analysis is widely recognized as the most important global event for semiconductor failure analysis, advanced packaging, and microelectronics reliability. The 2025 symposium focused on the growing complexity of advanced packaging, heterogeneous computing, chiplet architectures, and 2.5D and 3D integration. As device structures become more layered and material stacks more diverse, labs face rising demands on sample preparation and analytical workflows.
This year’s theme, “Scaling Beyond Moore’s Law: Heterogeneous Computing and Advanced Packaging,” highlighted the need for efficient preparation methods that support dense interconnects and mixed materials. The discussion centered on practical ways to maintain accuracy and workflow speed as device geometries shrink.
Two keynotes explored how design and policy shifts shape failure analysis needs. Dr. Raja Swaminathan of AMD addressed AI hardware and chiplet design, emphasizing interconnect density and power efficiency. Steven Herschbein outlined how U.S. semiconductor investments under the CHIPS Act strengthen manufacturing and analytical capability. Both emphasized the importance of rapid, reliable sample preparation.
ISTFA 2025 covered nineteen technical topic areas. Key categories included AI-assisted failure analysis, automated defect detection, advanced microscopy for material and structural characterization, FIB circuit editing and sample preparation, power device analysis with SiC and GaN, fault isolation at die and package levels, heterogeneous integration and 3D device reliability, hardware security and counterfeit detection, and optical fault isolation for complex architectures.
User groups for FIB, nanoprobing, sample preparation, AI applications, optical fault isolation, and system-in-package diagnostics shared practical techniques for working with complex structures. Many engineers noted that traditional tools require more adjustment as material stacks diversify.
More than one hundred exhibitors demonstrated technologies ranging from laser micromachining to advanced electron microscopy. Attendees focused on solutions that improve throughput and reduce material-specific tuning. Interest in laser-based sample preparation was steady throughout the hall.
Among these exhibitors, Tescan drew notable attention for demonstrating practical advances in laser preparation workflows.
Tescan focused on how FemtoChisel and Orage 2 address everyday challenges in semiconductor sample preparation. Based on internal figures, engagement during the two-day live demonstration period was among the strongest at the event.
Tescan delivered fifteen live sessions. Thirteen were booked before the show, and the remaining two were filled immediately onsite. Each demo session included small groups of engineers, analysts, or lab managers evaluating how the new laser systems could simplify their preparation steps.
Attendees consistently noted the debris-free cross sections with exceptional clarity that FemtoChisel provides. For many mid-scale applications, the cuts were clean enough to reduce or remove the need for extensive FIB polishing. This helped shorten downstream preparation tasks.
For nanoscale studies requiring FIB finishing, FemtoChisel provided a clean initial interface. Engineers commented that this starting point can reduce FIB polish time and support higher-throughput workflows.
As semiconductor devices increasingly use heterogeneous-material stacks, engineers value tools that minimize the need for repeated fluence adjustments. FemtoChisel uses higher fluence levels to ensure uniform material removal across different substances. The glass display sample demonstrated this effectively.
Discussions with users reflected a shared interest in preparation tools that combine stability, precision, and adaptability for new device architectures.
Orage 2 also earned positive feedback for applications such as package opening, high-speed material removal, TSV exposure, and structural access before FIB. When paired with FemtoChisel, Orage 2 supports integrated workflows designed to reduce bottlenecks and maintain sample consistency.
Attendees evaluated FemtoChisel and Orage 2 as practical options for advanced semiconductor sample preparation.
Analysts emphasized that clean sections reduce follow-on steps, especially in workflows that include both laser and FIB.
Consistent performance on mixed materials resonated with engineers working on advanced packaging.
Users saw clear value in combining laser speed with FIB precision to handle complex structures efficiently.
High participation in demos reflected active interest in improving preparation efficiency.
ISTFA 2025 highlighted the need for preparation methods that keep pace with advanced packaging, chiplet architectures, and heterogeneous materials. Tescan’s demonstrations showed how FemtoChisel and Orage 2 support these demands through cleaner cross-sections, consistent material performance, and integrated workflows that reduce preparation time.
This year’s event confirmed a broader industry direction: labs are seeking faster, clearer, and more adaptable ways to prepare complex semiconductor samples. Tescan’s approach aligned with that need, helping users work with confidence as device architectures continue to evolve.