TEM lamella alignment is essential for reliable transmission electron microscopy analysis, especially when the region of interest does not include a crystalline substrate that can guide zone-axis orientation. This workflow explains how an auxiliary silicon reference window can support accurate lamella orientation in semiconductor samples with tungsten contacts, gates, and dielectric layers.
In microelectronics, devices are typically built on a substrate with differently doped areas, overlayed with gates to control the current flow. Gates are then interconnected by multiple layers of metallization, separated by dielectric layers. A structural defect leads to device failure or affects performance. TEM lamella preparation makes it possible to investigate the region of interest at high resolution.
To obtain reliable TEM measurements, the lamella usually needs to be oriented to the zone axis, often using the monocrystalline substrate as a reference. This orientation is necessary to reach atomic-resolution imaging, accurate layer-thickness measurements, and clear layer contrast without imaging artifacts.
Image 1 shows a 30 keV STEM image of a TEM lamella from an Intel 32nm chip, including the Si substrate, gates, W contacts, and lines of the first metallization layer. In this example, the silicon substrate provides a clear reference for orienting the lamella in TEM.
Sometimes, the expected defect is not located on the substrate. To localize it, a plain-view lamella parallel to the substrate must be prepared at a specific device level. Image 2 shows a TEM lamella prepared from a smartphone camera image sensor at the level of the gate contacts, which connects the first metallization layer with the gates and are surrounded by dielectric. At this point, there are two possible preparation tasks, depending on the expected location of the defect. In one case, the silicon substrate is removed completely from the back side, leaving only tungsten contacts and dielectric within the lamella. In that situation, no silicon remains available to orient the lamella. In the second case, when it is preferable to keep the gates and part of the substrate, the silicon substrate is thinned on the back side to approximately 100-200 nm.
In this example, the lamella thickness is approximately 700 nm, including around 200 nm of remaining silicon and 500 nm of dielectric. As a rule of thumb, the amorphous layer in a lamella should not exceed 20% of the total lamella thickness. Traditionally, “amorphous” refers to the damaged layer induced by FIB polishing, but in this case, it refers to the amorphous dielectric layer. Although the high acceleration voltage of a TEM can still produce a good image of this lamella, it can be difficult to obtain a diffraction pattern from silicon when it is hidden by a large portion of dielectric. To provide a clear reference for orienting the lamella to the zone axis, a small area adjacent to the main thinned region can be used to open a second auxiliary window, which is polished until only the silicon substrate remains. Image 3 shows the final view of the lamella from Image 2, in which the leftmost 2 microns were polished further until they consisted solely of silicon, with a residual thickness of approximately 150 to 200 nm.
Image 4 shows an overview bright field STEM image of the lamella in TENSOR with its diffraction image. The diffraction image indicates that the lamella is correctly oriented in the zone axis using a silicon substrate. Image 5 shows a STEM bright field image of a lamella detail after alignment in the zone axis. Together, these views show how the reference window supports zone-axis alignment when the region of interest does not provide a clear crystalline reference.
Written by Maksym Klymov
Head of Applications Department, Tescan